The present invention relates to integrated circuit devices and, more particularly, to flash type memory integrated circuit devices and methods of forming the same.
A NOR type flash memory device typically including a cell array having a plurality of cell transistors disposed along rows and columns, word lines, and bit lines. A word line generally connects to gate electrodes of the cell transistors in a row direction (or a column direction) connected in parallel and a bit line generally connects to a drain region of the cell transistors in a column direction (or a row direction) connected in parallel. Such a NOR type flash memory device typically selects a cell transistor by a word line and a bit line. A decoder may be placed around the cell array that includes a plurality of transistors used to select the word line and the bit line.
FIG. 1 is an equivalent circuit diagram illustrating a cell array and a decoder in a conventional NOR type flash memory. As shown in FIG. 1, the NOR type flash memory device includes a cell array 10, a decoder 20 for selecting a word line and a decoder 30 for selecting a bit line. The cell array 10 includes a plurality of cell transistors Tc. A plurality of selection transistors Y1˜Yi arranged in a pyramid structure or a tree structure so as to facilitate selection of a bit line. With respect to each bit line (vertically extending in FIG. 1), groups of the plurality of cell transistors Tc are connected in series and electrically connected to a corresponding one of the bit lines.
The illustrated flash memory device typically includes high voltage transistors because high voltage operation is generally required. For example, as a source of a transistor connected to a bit line is typically boosted with a well bias in an erasing operation, a high junction breakdown voltage is generally desired. The high voltage transistors may be formed to have a low doped drain (LDD) structure or a double diffused drain (DDD) junction structure including a heavily doped diffusion layer and a lightly doped diffusion layer and the heavily doped diffusion layer may be formed separated from the gate electrode in order to provide a high breakdown voltage.
If the heavily doped diffusion layer is separated from the gate electrode, the breakdown voltage may be increased and a punch through may be suppressed. However, as an area ratio of the heavily doped diffusion layer may be reduced, an amount of saturation current may be decreased. A decrease of the saturation current of the high voltage selection transistors Y1˜Yi connected between the bit lines and the sense amplifier 40 may reduce a margin for reading a logic value of a cell transistor Tc. A saturation current of the high voltage transistors Y1˜Yi connected between the bit line and the sense amplifier 40 may increase in proportion to a channel width of the transistor and/or an area of a source/drain thereof, but an area for the transistor connected between the bit line and the sense amplifier generally can only be increased to a limited amount. In particular, only a single selection transistor is directly connected to each bit line as shown in FIG. 1, so the ability to increase the area is generally restricted.